Non-volatile data storage devices, such as universal serial bus (USB) flash memory devices, removable storage cards, or solid state drives (SSD), have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g. “parity bits”) that may be stored with the data. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases. An ECC decoder can be complex and challenging to design, debug, and implement.
Multi-phase ECC can include a first phase of ECC decoding using a reduced set of parity bits for individual chunks of data and a second phase of ECC decoding using a larger set of parity bits. The larger set of parity bits can be used for more powerful decoding of a chunk that is not decodable using the reduced set of parity bits. The larger set of parity bits need not be stored for each individual chunk of data but may instead by generated for one or more chunks based on other chunks that have been successfully decoded. Because of the multiple decoding phases, implementation of a multi-phase ECC decoder can be more complex and more challenging to design, implement, and debug than a single-phase ECC decoder.